1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device package composed of an semiconductor device chip mounted on a circuit substrate having a plurality of external electrodes formed thereon.
2. Description of Related Art
Referring to FIG. 1, there is shown a diagrammatic sectional view of one example of the prior art semiconductor device package. The shown prior art example includes a semiconductor device chip 37 mounted on a circuit substrate 31 and encapsulated with a resin 30. A plurality of end-face through-hole electrodes 33 in the form obtained by axially halving a circular solid column at its center axis, are formed at each end face of the rectangular substrate 33. This type of semiconductor device package is known as a LCC or LLCC (leadless chip carrier) type package. This LCC package is disclosed by for example Japanese Patent Application Pre-examination Publication No. JP-A-05-327157 (the content of which is incorporated by reference in its entirety into this application, and also an English abstract of JP-A-05-327157 is available from the Japanese Patent Office and the content of the English abstract of JP-A-05-327157 is also incorporated by reference in its entirety into this application). In this example, the end-face electrodes are formed by halving the end-face through holes of a ceramic multilevel interconnection substrate. At the time of mounting this type package on a circuit board, the mounting and an electrical connection are realized by forming a solder wetted surface extending from an inner surface of the end-face halved through-hole to a rear face electrode of the package, by use of a solder mainly composed of lead-tin (Pb--Sn) alloy. In another example, a printed circuit board is used as the substrate.
Referring to FIG. 2, there is shown a diagrammatic sectional view of a further example of the prior art semiconductor device package. A semiconductor device chip 47 is mounted on a circuit substrate 41 and is encapsulated with a resin 40. Wiring conductors 42 formed on an upper surface of the substrate 41 and connected to the semiconductor device chip 47 through bonding wires 48, are electrically connected to conductors 45 formed on a lower surface of the substrate 41 by through holes 11a formed to penetrate the substrate 41. A solder resist 44 is partially coated on the lower surface conductors 45 to confine a solder repelling area, and on the other hand, a solder is deposited on an inner end of each of the lower surface conductors 45, to form a solder projection electrode 46 as an external electrode at the inner end of each lower surface conductor 45. When the solder projection electrode 46 is formed, since a solder ball is used, this package is recently well known as a BGA (ball grid array) package.
In the prior art semiconductor device package shown in FIG. 1, since the substrate end-face electrodes are formed on only the periphery of the substrate, the number of electrodes provided in the package is liable to come short. In the case of attempting to increase the number of electrodes, the pitch of the end-face electrodes must be narrowed. However, this is difficult since the spacing between adjacent end-face electrodes must be sufficiently ensured because the end-face electrodes is wettable to solder. In addition, if the spacing between adjacent end-face electrodes is narrowed, since the end-face electrodes is wettable to solder, the packaging also becomes difficult.
On the other hand, in the BGA type semiconductor device package shown in FIG. 2, it is necessary to ensure a minimum electrode pitch when the external electrodes are formed of the solder ball and the package is mounted on a printed circuit board. Therefore, at the time of attempting to increase the number of electrodes, it becomes difficult to miniaturize the package.